eight-output, 200-mhz zero delay buff er cy2308 a cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-07377 rev. *c revised march 5, 2003 features ? 50-mhz to 200-mhz operating range 650-ps total timing budget ? (ttb ? ) window multiple configurations (see table 2 ) eight low-skew outputs ? output-output skew < 200 ps ? device-device skew < 500 ps input-output skew < 250 ps three-stateable outputs < 50- a shutdown current phase-locked loop (pll) bypass mode (see table 1 ) spread aware ? 16-pin tssop 3.3v operation commercial/industrial temperature functional description the cy2308a is a high-performance 200-mhz zero delay buffer designed for high-speed clock distribution. the integrated pll is designed for low jitter and optimized for noise rejection. these parameters are critical for reference clock distribution in systems using high-performance asics and microprocessors. the cy2308a pll feedback is external and is required to be driven into the fbk pin using anyone of the outputs. the device features a guaranteed maximum ttb window specifying all occurrences of output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process. the cy2308a has two banks of four outputs each that can be controlled by the select inputs as shown in table 1 . if all output clocks are not required, bank b can be three-stated. the select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. the cy2308a pll enters a power-down state when there are no rising edges on the ref input. in this mode, all outputs are three-stated and the pll is turned off, resulting in less than 50 a of current draw. the pll shuts down in two additional cases, as shown in table 1 . the cy2308a is available in five different configurations, as shown in table 2 . the cy2308a?1 is the base part with the output frequencies equal to the reference if there is no divider in the feedback path. the cy2308a?1h is the high-drive version of the ?1 with faster rise and fall times. the cy2308a?2 allows the user to obtain 1x / ?x frequencies on each output bank. the exact configuration and output frequencies depends on which output drives fbk. 9 16 fbk clka1 clka2 v dd gnd clka3 clka4 s1 block diagram 1 2 3 4 5 6 7 8 10 11 12 13 14 15 ref clkb1 clkb2 v dd gnd clkb3 clkb4 s2 tssop top view pin configuration ref clka1 clka2 clka3 clka4 fbk pll mux select input decoding s2 s1 clkb1 clkb2 clkb3 clkb4 /2 extra divider (?2)
cy2308 a document #: 38-07377 rev. *c page 2 of 8 pin description pin signal description 1 ref input reference frequency, 5v-tolerant input 2 clkb1 [2] clock output, bank b 3 clkb2 [2] clock output, bank b 4v dd 3.3v supply 5 gnd ground 6 clkb3 [2] clock output, bank b 7 clkb4 [2] clock output, bank b 8s2 [1] select input, 5v-tolerant input 9s1 [1] select input, 5v-tolerant input 10 clka4 [2] clock output, bank a 11 clka3 [2] clock output, bank a 12 gnd ground 13 v dd 3.3v supply 14 clka2 [2] clock output, bank a 15 clka1 [2] clock output, bank a 16 fbk pll feedback input table 1. select input decoding s2 s1 clock a1?a4 clock b1?b4 output source pll shutdown 0 0 three-state three-state pll y 0 1 driven three-state pll n 1 0 driven driven reference y 1 1 driven driven pll n table 2. available cy2308a configurations device feedback from bank a frequency bank b frequency cy2308a?1 bank a or bank b reference reference cy2308a?1h bank a or bank b reference reference cy2308a?2 bank a reference reference/2 cy2308a?2 bank b reference x2 reference notes: 1. weak pull-up. 2. weak pull-down.
cy2308 a document #: 38-07377 rev. *c page 3 of 8 maximum ratings supply voltage to ground potential ............... ?0.5v to +7.0v dc input voltage (except ref, s1, s2) ..............................?0.5v to v dd + 0.5v dc input voltage (ref, s1, s2) .............................?0.5 to 7v storage temperature .................................. ?65c to +150c junction temperature .................................................. 125c junction-to-ambient thermal resistance 16-pin tssop ......................................................... 115c/w static discharge voltage (per mil-std-883, method 3015) ............................ > 2000v table 3. operating conditions for cy2308azc?xx commercial temperature devices parameter description min. max. unit v dd supply voltage 3.135 3.465 v t a operating temperature (ambient temperature) 0 70 c c in input capacitance 7 pf t pu power-up time for all vdds to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms table 4. electrical characteristics for cy2308azc?xx commercial temperature devices parameter description test conditions min. max. unit v il input low voltage cmos levels, 30% of v dd 0.25 v dd v ih input high voltage cmos levels, 70% of v dd 0.7 v dd i il input low current v in = 0v 50.0 a i ih input high current v in = v dd 10.0 a i ol output low current [3] (?1, ?2) v ol = 0.5v 12 ma (?1h) 18 i oh output high current [3] (?1, ?2) v oh = v dd ? 0.5v ?12 ma (?1h) ?18 i dds power-down supply current ref = 0v, s1 = v dd , s2 = v dd 50 a i dd supply current unloaded outputs @ 200 mhz 115 ma loaded outputs @ 200 mhz, c l = 10 pf 145 table 5. switching characteristics for cy2308azc?xx commercial temperature devices [4] parameter name test conditions min. typ. max. unit reference frequency 50 200 mhz reference edge rate 30% to 70% of v dd 0.5 4 v/ns reference duty cycle 25 75 % t 1 output frequency c l = 10 pf 50 200 mhz c l = 15 pf 50 140 mhz duty cycle [3] = t 2 t 1 measured at v dd /2 45.0 50.0 55.0 % t 3 rising edge rate [3] (?1, ?2) 20% to 80% of v dd , c l = 15 pf 0.8 4 v/ns rising edge rate [3] (?1h) 20% to 80% of v dd , c l = 15 pf 1 4 v/ns t 4 falling edge rate [3] (?1, ?2) 80% to 20% of v dd , c l = 15 pf 0.8 4 v/ns falling edge rate [3] (?1h) 80% to 20% of v dd , c l = 15 pf 1 4 v/ns t tb ttb window, bank a and b same frequency [5] outputs @ 200 mhz, tracking skew not included 650 ps ttb window, bank a and b different frequency [5] 850 notes: 3. parameter is guaranteed by design and characterization. not 100% tested in production. 4. all parameters are specified with loaded outputs. 5. t tb is the window between the earliest and the latest output clo cks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input clock edge rate, and process. the measurements are taken with the ac test load specified and inclu de output-output skew, cycle- cycle jitter, and dynamic phase error. t tb will be equal to or smaller than the maximum specified value at a given output frequency.
cy2308 a document #: 38-07377 rev. *c page 4 of 8 t 5 output-to-output skew [3] all outputs equally loaded 200 ps t 6 input-to-output skew (static phase error) [3] measured at v dd /2, ref to fbk 250 ps t 7 device-to-device skew [3] measured at v dd /2 500 ps t j cycle-to-cycle jitter, [3] bank a and b same frequency loaded outputs 200 ps 35 ps rms cycle-to-cycle jitter, [3] bank a and b different frequency loaded outputs 400 ps 70 ps rms t lock pll lock time [3] stable power supply, valid clock at ref 1.0 ms table 6. operating conditions for cy2308azi?xx industrial temperature devices parameter description min. max. unit v dd supply voltage 3.135 3.465 v t a operating temperature (ambient temperature) ?40 85 c c in input capacitance 7 pf t pu power-up time for all vdds to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms table 7. electrical characteristics for cy2308azi-xx industrial temperature devices parameter description test conditions min. max. unit v il input low voltage cmos levels, 30% of v dd 0.25 v dd v ih input high voltage cmos levels, 70% of v dd 0.7 v dd i il input low current v in = 0v 50.0 a i ih input high current v in = v dd 10.0 a i ol output low current [3] (?1, ?2) v ol = 0.5v 10 ma (?1h) 15 i oh output high current [3] (?1, ?2) v oh = v dd ? 0.5v ?10 ma (?1h) ?15 i dds power-down supply current ref = 0v, s1 = v dd , s2 = v dd 50 a i dd supply current unloaded outputs @ 133 mhz 80.0 ma loaded outputs @ 133 mhz, c l = 10 pf 110.0 table 8. switching characteristics for cy2308azi?xx industrial temperature devices [4] parameter name test conditions min. typ. max. unit reference frequency 50 133 mhz reference edge rate 30% to 70% of v dd 0.5 4 v/ns reference duty cycle 25 75 % t 1 output frequency c l = 10 pf 50 133 mhz duty cycle [3] = t 2 t 1 measured at v dd /2 40.0 50.0 60.0 % t 3 rising edge rate [3] (?1, ?2) 20% to 80% of v dd , c l = 15 pf 0.5 3 v/ns rising edge rate [3] (?1h) 20% to 80% of v dd , c l = 15 pf 0.8 4 v/ns t 4 falling edge rate [3] (?1, ?2) 80% to 20% of v dd , c l = 15 pf 0.5 3 v/ns falling edge rate [3] (?1h) 80% to 20% of v dd , c l = 15 pf 0.8 4 v/ns table 5. switching characteristics for cy2308azc?xx commercial temperature devices [4] (continued) parameter name test conditions min. typ. max. unit
cy2308 a document #: 38-07377 rev. *c page 5 of 8 ref. input to clka/clkb delay vs. difference in loading between fbk pin and clka/clkb pins zero delay and skew control to close the feedback loop of the cy2308a, the fbk can be driven from any of the eight available output pins. the output driving the fbk will be driving a total load of 7 pf plus any additional load that it drives. the relative loading of this output (with respect to the remaining outputs) can adjust the input- output delay. see ref input to clk delay vs. loading difference . for applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. if input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. for zero output-output skew, be sure to load outputs equally. for further information on using cy2308a, refer to the appli- cation note cy2308: zero delay buffer . t tb total timing budget window, bank a and b same frequency [5] outputs @ 133 mhz, tracking skew not included 650 ps total timing budget window, bank a and b different frequency [5] 850 t 5 output-to-output skew [3] all outputs equally loaded 200 ps t 6 input-to-output skew (static phase error) [3] measured at v dd /2, ref to fbk 250 ps t 7 device-to-device skew [3] measured at v dd /2 500 ps t j cycle-to-cycle jitter [3] , bank a and b same frequency loaded outputs 200 ps 35 ps rms cycle-to-cycle jitter [3] , bank a and b different frequency loaded outputs 400 ps 70 ps rms t lock pll lock time [3] stable power supply, valid clock at ref 1.0 ms table 8. switching characteristics for cy2308azi?xx industrial temperature devices [4] (continued) parameter name test conditions min. typ. max. unit
cy2308 a document #: 38-07377 rev. *c page 6 of 8 test circuits switching waveforms duty cycle timing t 1 t 2 v dd /2 v dd /2 v dd /2 0.1 f v dd 0.1 f v dd clk out c load outputs gnd gnd test circuit all outputs rise/fall time output t 3 vdd 0v 20% 80% 80% 20% t 4 output-output skew v dd /2 v dd /2 t 5 output output input-output propagation delay v dd /2 t 6 input output v dd /2 v dd /2 v dd /2 t 7 fbk, device 1 fbk, device 2 device-device skew ordering information ordering code package type operating range cy2308azc-1 16-pin 4.4-mm tssop commercial, 0c to 70c cy2308azc?1t 16-pin 4.4-mm tssop ? tape and reel commercial, 0c to 70c cy2308azc?1h 16-pin 4.4-mm tssop commercial, 0c to 70c cy2308azc?1ht 16-pin 4.4-mm tssop ? tape and reel commercial, 0c to 70c cy2308azc?2 16-pin 4.4-mm tssop commercial, 0c to 70c cy2308azc?2t 16-pin 4.4-mm tssop ? tape and reel commercial, 0c to 70c cy2308azi-1 16-pin 4.4-mm tssop industrial, ?40c to 85c cy2308azi-1t 16-pin 4.4-mm tssop ? tape and reel industrial, ?40c to 85c
cy2308 a document #: 38-07377 rev. *c page 7 of 8 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram spread aware, total timing budget, and ttb are trademarks of cypress semiconductor. all product and company names mentioned in this document may be the trademarks of their respective holders. cy2308azi?1h 16-pin 4.4-mm tssop industrial, ?40c to 85c cy2308azi?1ht 16-pin 4.4-mm tssop ? tape and reel industrial, ?40c to 85c cy2308azi-2 16-pin 4.4-mm tssop industrial, ?40c to 85c cy2308azi-2t 16-pin 4.4-mm tssop ? tape and reel industrial, ?40c to 85c ordering information (continued) ordering code package type operating range 16-lead thin shrunk small outline package (4.40 mm body) z16 51-85091-**
cy2308 a document #: 38-07377 rev. *c page 8 of 8 document history page document title: cy2308a eight-output, 200-mhz zero delay buffer document number: 38-07377 rev. ecn no. issue date orig. of change description of change ** 112938 04/02/02 ctk new data sheet *a 114685 07/17/02 hwt change freq. of operation to 50 mhz?200 mhz eliminate specification related to 30-pf load *b 121892 12/14/02 rbi power-up requirements added to operating conditions information *c 124597 03/06/03 rgl changed v il max value in commercial temp. device from 0.3v to 0.25v changed i dd max values in commercial temp. device from 75 and 150 to 115 and 145 ma, respectively changed v il max value in industrial temp device from 0.3v to 0.25v changed i dd max value in industrial temp device from 60 and 120 ma to 80 and 110 ma removed preliminary (final data sheet)
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